Honored Contributor
Honored ContributorKevin,
You are right about delaying the second write causes the data lost. Although I'm using the DDR controller the case were the same, I tried to simulate and I found out that if the write burst size is 2 and if the 2nd write will be on the 6th or more clock cycle after the 1st write the data will be lost. But, the reply from altera support said that in Avalon-MM interface the write should be done consecutively. Here is the reply from altera support. ------------------------------------ Generally, if you want to use Avalon-MM interface for DDR controller, you need to write local logics which meet Avalon-MM protocol. Since the local_size is 2, the local logics need to generate two continuous local_write_request with one local_burstbegin. I modify ddr_controller_test.v and get the simulation result which is similar to the figure in the User Guide. ------------------------------------- Anyway, thank you for your reply I was able to resolved the problem from your post before the altera support replied because they ask me create and send the archived project that emulate the problem for there investigation. Zeahr
