Honored ContributorHi ,
i would like to make sure i understand how to set the burst begin signal in full rate avalon-mm interface to the DDR controller. i understand that when writing 64 bits i should assert the burst begin signal for one clock cycle with the burst. when writing only 32 bits burst size is 1 , i don't assert the burst begin signal is this correct? thanks
Honored ContributorAre you creating your own master to use in SOPC Builder/Qsys? If so you don't need to worry about driving this signal. The fabric will generate the burst begin at the appropriate time for you.
If you are using the memory controller in a stand alone fashion with an Avalon-MM local interface, you should strobe the burst begin even if you drive a burst length of 1 into the memory controller. Also the burstbegin signal does not heed waitrequest (local_ready == 0) so if the memory controller is not ready you shouldn't send another burstbegin. To learn more refer to the Avalon specification: http://www.altera.com/literature/manual/mnl_avalon_spec.pdfHonored Contributor
