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Altera_Forum
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10 years ago

DCFIFO: shoud i set flase path timing

HI, Im using a DCFIFO (dual clock fifo) to transfer clock domains. i genreated a DCFIFO, but i get timing violations from 1 clock to the other regards Fifo components. should i "set_f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

the output latency of usedw depends on parameter settings. It can be more than one rd- or wr-clock. Please refer SCFIFO and DCFIFO IP Cores User Guide.