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Altera_Forum
Honored Contributor
10 years agoDCFIFO: shoud i set flase path timing
HI, Im using a DCFIFO (dual clock fifo) to transfer clock domains. i genreated a DCFIFO, but i get timing violations from 1 clock to the other regards Fifo components. should i "set_f...
Altera_Forum
Honored Contributor
10 years agoHi,
thanks for all your comments. so just to be sure, its ok to write on the SDC file : set_false_path -from [get_clocks {clka}] -to [get_clocks {clkb}] set_false_path -from [get_clocks {clkb}] -to [get_clocks {clka}] when i have a dcfifo crossing the clock domain?