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Altera_Forum
Honored Contributor
Honored ContributorDCFIFO: shoud i set flase path timing
HI, Im using a DCFIFO (dual clock fifo) to transfer clock domains. i genreated a DCFIFO, but i get timing violations from 1 clock to the other regards Fifo components. should i "set_f...
Altera_ForumHonored Contributor
Honored ContributorI believe there are some recommended timing constraints to use with dcfifo's that might help, see:
page 20 of ug_fifo.pdf "Embedded constraint settings"
