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Honored Contributor
Honored ContributorDCFIFO rdusedw and rdreq
Dear All, I've instantiated a DCFIFO (Cyclone II). The read and write clocks are not synchronized to each other. I'm using a signal synchronized to the rdclk as the rdreq which is approxim...
Altera_ForumHonored Contributor
Honored ContributorThe rdreq signal is high only for one clock duration (of the rdclk) and low for the remaining four clocks.
I understand that the rdusedw is updated with the rdclk. I also understand that the rdreq is just used as a read enable and there is no significance of it's edge. But what I expect is that the rdusedw should get updated when something is 'read' from the read port, not at other clock cycles of rdclk. Nagaraj
