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Altera_Forum
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16 years ago

DCFIFO rdusedw and rdreq

Dear All, I've instantiated a DCFIFO (Cyclone II). The read and write clocks are not synchronized to each other. I'm using a signal synchronized to the rdclk as the rdreq which is approxim...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I'm not sure I understand. If you assert rdreq for five rdclk cycles, you will see the rdusedw decrement by a value of 5. Everything is based off of the clock. rdreq is not an edge-detect signal. A read is performed at every clock cycle where rdreq is asserted.

Jake