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Altera_Forum
Honored Contributor
16 years agoDCFIFO rdusedw and rdreq
Dear All,
I've instantiated a DCFIFO (Cyclone II). The read and write clocks are not synchronized to each other. I'm using a signal synchronized to the rdclk as the rdreq which is approximately 5 times slower than the rdclk (I can't use my rdreq itself as a clock for other reasons). What I observe in SignalTap is that the rdusedw is updated at a higher frequency than that of my rdreq.
I understand that in a DCFIFO, rdusedw is derived from the read pointer. In that case shouldn't it get updated at the rdreq ? Is there anything I'm mising? P.S.: I'm using rdclk as the SignalTap sampling clock.
6 Replies
- Altera_Forum
Honored Contributor
The rdusedw is the number of words in fifo as seen in rd clk domain
- Altera_Forum
Honored Contributor
I'm not sure I understand. If you assert rdreq for five rdclk cycles, you will see the rdusedw decrement by a value of 5. Everything is based off of the clock. rdreq is not an edge-detect signal. A read is performed at every clock cycle where rdreq is asserted.
Jake - Altera_Forum
Honored Contributor
Also, please try to post your questions only in one section of the forum. It's difficult to have a discussion in multiple places.
Jake - Altera_Forum
Honored Contributor
The rdreq signal is high only for one clock duration (of the rdclk) and low for the remaining four clocks.
I understand that the rdusedw is updated with the rdclk. I also understand that the rdreq is just used as a read enable and there is no significance of it's edge. But what I expect is that the rdusedw should get updated when something is 'read' from the read port, not at other clock cycles of rdclk. Nagaraj - Altera_Forum
Honored Contributor
When you say "updated", do you mean rdusedw is decreased?
- Altera_Forum
Honored Contributor
--- Quote Start --- But what I expect is that the rdusedw should get updated when something is 'read' from the read port, not at other clock cycles of rdclk. Nagaraj --- Quote End --- The number of fifo words can change by either a write or read operation. The wrusedw is updated synchronised to wr clk, shortly the rdusedw is updated synchronised to rd clk irrespective of rdreq