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Altera_Forum
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13 years ago

DCFIFO Megafunction simulation problem

Hi, I am attempting to use DCFIFO megafunction in my design, but i can't get it running!! The input data to be written to FIFO is (45 bit parallel) streaming video data clocked at 5MHz (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi, did you solve the problem?

following is my problem:

when I generated a DCFIFO with read clock different from writing clock, the rdempty signal always keep high, and rdusew signals don't function, too. so I can't read data from FIFO. after checking the wrempty and wrusew signals, they function correctly, so I use wrusew to detect and correctly got the desired. following is my verilog:

https://www.alteraforum.com/forum/attachment.php?attachmentid=14816

https://www.alteraforum.com/forum/attachment.php?attachmentid=14817

https://www.alteraforum.com/forum/attachment.php?attachmentid=14818

so my qustions are:

1. what is wrong with rd signals?

2. when using the same clock for both rd and wr clock, everything works fine(using either wrempty or wrusew to detect), but when rdclock is different from wrclock, either faster or slower, the data readout is not exactly what it received.