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** Maybe so, but the Qsys flow doesn't support a streaming interface to the pcie. It seems like a lot of work to put the pci express block outside of qsys and take care of flow control (credit processing must be done by hand) just to do dma, especially when my transactions are always the same length.
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I'd be careful which version of Quartus you're using.
I have a design which originated driving DMA on a PCI interface.
I migrated this to drive DMA on the Cyclone IV hard PCIe core with Quartus 11.0. This worked, except interrupts were broken in 11.0.
When 11.1 was released the interrupts worked, but I have been getting holes in the data that's been DMA'd to the host memory. If I generate my project Qsys system then build the FPGA in 11.0 then DMA works, if I do the same, with the same project, in 11.1 then DMA is broken.
I've been discussing this off-line with Badomen but we weren't able to come up with a solution.
I was just about to submit an SR about this when I noticed earlier that Quartus 12.0 has been released. This appears to fix the problem.
So, with 11.0 the interrupts were broken and 11.1sp2 the DMA engine was broken, this doesn't give great confidence in Altera's quality control.
:mad:
So far 12.0 looks OK.
Nial
Honored Contributor
