Cyclone V hard memory controller clarification

Hi Lance,

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Thanks for commenting. No, I haven't simulated this part of the design yet. I'm sure it is good advice. I spent some time probing the avalon interconnects and DDR controller signals and it got pretty cumbersome in signaltap, so that is probably the way to go if I need to get above 80% efficiency. I've not yet simulated blocks that contain altera IP (though have simulated many blocks that I wrote). That is definitely on my list that I've not gotten to yet.

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I've been trying to get around to writing up my "Altera Memory Interfacing" notes into a tutorial. While I was making those notes I found a problem with the Cyclone V DDR3 controller and the various reset controls it uses. I wrote a testbench and submitted an Altera Service Request, and as far as I recall, its basically sitting in their bug-fix queue. The bug does not affect you, but the point is, that its not that hard to simulate the Cyclone V DDR3 interface. I'll try to get around to writing up those notes, and you can go through them.

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My post probably should have been titled "is there a way to predict" or "can anyone share their experiences with" the memory controller throughput under simplified conditions.

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The answer will be "no" for any controller. Its all black-box IP, and that IP has configuration parameters (eg., refresh rate), and so there is no one answer to the question. The answer is "simulate it" and see if it meets your requirements.

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I can survive for now with the efficiency I'm getting and need to prioritize other tasks. I was hoping to get some feedback on any fundamental barriers I would face when trying to achieve high memory throughput efficiency with fixed write-only transfers from one port.

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Sounds good. When you want to look at simulation, ping me, and at a minimum I can send you the Cyclone V files I submitted for the Service Request.

Cheers,

Dave