Cyclone V hard memory controller clarification

Not sure if anybody will have that specific information for you, but it is easy enough to test your hypothesis by putting SignalTap on the Avalon-MM ports and look at how the transactions are getting broken up.

I'm not sure, but as far as that knowledge base article goes, I believe a "4 clock cycle command" would be initiating a long burst. So you might have many cycles of activity before hitting the 1 cycle for the described port polling. I don't think that article is stating that 1 out of 5 clocks is lost (the 80% you are seeing).