Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoHi Johnson,
Thanks for your update. As I understand it, you are observing Fitter error when you try to use different refclks for the SDI RX instances. Just would like to check with you in your initial design which passed compilation, how many MPLL has been used? You may check with the Fitter report to see if both of the MPLLs have been utilized even when you are using single refclk for 2 RX and 1 TX?
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
JLee25
Contributor
6 years agoHi Chee Pin,
1 MPLL has been used in 2Rx and 1Tx, PLL_5.
Also the SDI Tx uses a GPLL, PLL_1.
There's only 1 PLL left in the design.
The clock pin was M11/ N11 for this.
I have another clock locates at M7/ N7.
But can't be used in fitter.
FYI!
BRs,
Johnson