Cyclone III DDR2 HPCII burst problem

Hi all,

Currently I have some problem of utilizing HPCII burst. My configurations are listed below:

PLL reference clock frequency: 75MHz

Memory clock frequency: 150MHz

Controller data rate: Half

Local interface clock frequency: 75MHz

Local interface width: 128 bits

Total memory interface DQ width: 32 bits

Memory burst length: 8 beats

Controller architecture: HPCII

Local-to-Memory Address Mapping: CHIP-ROW-BANK-COL

Local Maximum Burst Count: 16

I wrote the Avalon-MM master local side control logic by myself, and it has output of local_burstcount[4:0], which should match "Local Maximum Burst Count: 16" on HPCII side. When I connected my Avalon-MM local side master with HPCII in SOPC builder and generated Verilog simulation model, I observed that in the arbitrator generated by SOPC builder, it always set the burst count to 1 instead of connecting local_size[4:0] port of HPCII to local_burstcount[4:0] port in my Avalon-MM master:

//burstcount mux, which is an e_mux

assign altmemddr_0_s1_burstcount = 1;

Due to the above assignment, my HPCII local_size[4:0] is always 1 no matter what value is assigned on my Avalon-MM master local_burstcount[4:0] output. Therefore, there's no local burst on HPCII. How can I fix this problem and enable a local burst of value greater than 1?

Thanks!