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Altera_Forum
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15 years ago

Cyclone III, DDR2 HPCII and timing

Trying to simulate a Cyclone III/DDR2 controller @ 150MHz on the interface. Using a pair of Micron DDR2 (MT47H64M16-3) chips, along with Micron's Verilog model of same. Trying to sim the behavior w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Never mind. A wiring error on the address lines caused the intialization to mess up. Once fixed, the timing corrected.