Cyclone 10Gx PCIe Hard IP Avalon access speed

HI jbayl,

Ya, it's weird as your PCIe BW by right has been double from 2.5G to 5G. You may want to consult your software team on potential design changes.

• After all, you have upgrade from PCIe Gen 1 to Gen 2. The design cannot be the same. There must be some changes.

Max payload setting is a setting in PCIe hard IP itself.

• What do you set in the hard IP ? Does it show error if you set it to something >256 ?

For the max_read_request_size, this is bit [14:12] of PCIe spec capability register -> device control register at address 0x088.

• You can feedback to your software team and they should know how to change it

The other thing that you can feedback to your software team is PCIe user guide chapter 11 did mentioned about PCIe throughput optimization techniques done at software application layer. Check out below link page 108, chapter 11

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

Thanks.

Regards,

dlim