Cyclone 10Gx PCIe Hard IP Avalon access speed

Hi Dlim,

1. Yes, there should be performance boost if you look at the PCIe interface. But what we're measuring is showing the opposite. Our software team timed a pre-set transaction (serial data to/from UUT) to compare the Version1 performance with the Version2 board.

2. PCIe link width is x1 on both boards.

3. It's currently set to 256 bytes. I'll try increase it and let our SW team know.

4. Is this an FPGA/HardIP setting? I can't find it on the HIP parameters tab.

Thanks!

Regards,

jbayl