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JBayl
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5 years ago

Cyclone 10Gx PCIe Hard IP Avalon access speed

Hi, We upgraded our old PCIe Gen 1 board (NXP's PX1011B and Cyclone III) to a Cyclone 10Gx based board with the Hard IP configured at Gen2 64-bit 125Mhz. We've maintained the same SW (windows...
JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Dlim,

1. Yes, there should be performance boost if you look at the PCIe interface. But what we're measuring is showing the opposite. Our software team timed a pre-set transaction (serial data to/from UUT) to compare the Version1 performance with the Version2 board.

2. PCIe link width is x1 on both boards.

3. It's currently set to 256 bytes. I'll try increase it and let our SW team know.

4. Is this an FPGA/HardIP setting? I can't find it on the HIP parameters tab.

Thanks!

Regards,

jbayl

JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I'm getting a message on Platform Designer that 256 bytes is the maximum payload for an Avalon MM interface.