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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Cyclone 10Gx PCIe Hard IP Avalon access speed

Hi, We upgraded our old PCIe Gen 1 board (NXP's PX1011B and Cyclone III) to a Cyclone 10Gx based board with the Hard IP configured at Gen2 64-bit 125Mhz. We've maintained the same SW (windows...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Common factor that will affect PCIe performance is like below

  1. PCIe speed
  • Your old design is running with PCIe Gen 1 which is just 2.5GT/s
    • Now you already upgrade to PCIe Gen 2 which becomes 5GT/s
    • Byright you already enjoy performance boost but you are saying NO ?
  1. PCIe link width
  • Any changes on the link width between old design vs new design ?
    • x1, x4, x8 and etc ?
  1. Max payload size
  • have you tried to increase this setting ?
  1. Max read request size
  • have you tried to increase this setting ?


Thanks.


Regards,

dlim


JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi Dlim,

1. Yes, there should be performance boost if you look at the PCIe interface. But what we're measuring is showing the opposite. Our software team timed a pre-set transaction (serial data to/from UUT) to compare the Version1 performance with the Version2 board.

2. PCIe link width is x1 on both boards.

3. It's currently set to 256 bytes. I'll try increase it and let our SW team know.

4. Is this an FPGA/HardIP setting? I can't find it on the HIP parameters tab.

Thanks!

Regards,

jbayl

  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I'm getting a message on Platform Designer that 256 bytes is the maximum payload for an Avalon MM interface.