Forum Discussion
Hi,
From my understanding, you have a few questions related to transceiver (XCVR) power‑up calibration on the Cyclone® 10 GX device. To make sure we’re aligned, could you please share with me how you are measuring the calibration time in your setup (for example, which signals you are monitoring and from which point to which point the time is measured)?
Below are my responses to your questions:
1. Is a ~353 ms calibration time expected when using all 12 transceivers on this device family?
Based on available documentation, there is no specific, fixed calibration-time specification for Cyclone 10 GX devices. As stated in the Cyclone 10 GX Transceiver User Guide, calibration duration can vary by device.
Assuming:
- All clocks are stable & free-running prior device configuration, within specification, and
- All *_cal_busy signals deassert cleanly,
a ~353 ms calibration time would generally be considered expected behavior, rather than an anomaly.
2. Is transceiver calibration executed sequentially across multiple quads, or is full parallel calibration supported?
I do not have explicit visibility into whether calibration is fully parallel or strictly sequential across quads. However, based on general understanding, the calibration process appears to be a combination of parallel and sequential operations across different internal blocks.
As a result, designs using fewer channels (for example, 1 or 6 channels) would be expected to have shorter overall calibration times compared to designs using all 12 channels.
3. Are there recommended design practices to reduce power‑up calibration latency?
If you are currently using CLKUSR at 100 MHz, you may try increasing it to 125 MHz to see whether it helps reduce calibration time.
In addition, please ensure that:
- CLKUSR and all reference clocks are stable and free‑running before FPGA configuration begins
Please let me know if you have any follow-up questions. I’ll be happy to assist further.
Thank you.