Hello dlim, I modified the custom Dipalyport Receiver board. The Modified point is CLKUSR pin only DisplayPort Receiver function still doesn't work. I attached two picture. Picture 1 : cyclone 10gx transceiver PHY user Guide (20.1) page 259 Picture 1: I probing from my board. In my system, the rx_is_lockedtodata signal and rx_is_lockedtoref are always low (it is problem) Can you advice how to make it to work ? My concern is rx_cal_busy and rx_analogreset signal is overlapping (?) I didn't change anything in bitec-reconfig_alt_c10.v and xcve_reconfig_arbiter.sv. I checked all reconfiguration signals. it works good. the calibration step works good because rx_analogreset asserted. I think the PLL(rx_cdr_refclk0 : 135MHz) doesn't lock. Michael

Hello dlim, I attached two picture, it is for previous mail. I captured all reconfiguration interface address and data. It looks correct. The read and write operation repeated each channel but I captured only one channel. I think the CDR pll doesn't lock. I checked 135MHZ clock. it is ok Thanks Michael

Attached is the C10 CDR loose lock debug check list for your reference

Hi, ok, looks like transceiver calibration can be completed and it's not stuck in reset mode anymore I have 2 suggestion for you. You should isolate whether the CDR loose lock issue is caused by your board issue or your Quartus design issue. To rule out potential board issue : Perform FPGA transceiver channel internal loopback follow by external loopback on board FPGA transceiver channel internal loopback must works else there is really some issue with your board or the FPGA device itself or some manufacturing soldering contact issue You can perform internal loopback using transceiver toolkit. Reference design and user guide doc is available in below link https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/ Once you verified to get the internal loopback working, then you can move on to check with external loopback on your board. (assuming you can perform external loopback on your board) If it's failing with external loopback, then you can cross check the debug suggestion in CDR debug checklist that I shared with you in previous post To rule out potential Quartus design issue It would be best if you can just stick with using DisplayPort Rx to Tx example design to bring up the DP Rx first before you move on to make design modification on it Thanks. Regards, dlim

Hi dlim, I installed C10GX_toolkit_demo design kit and I got same result as mine. I probed internal signal as below pll_locked : always "L" : means doesn't locked locked : always " L" : this signal is IOPLL lock signal for test. but the 16MHZ clock comes out rx_is_lockedtodata : always "L" : same result as my design I attached C10GX_toolkit_demo design and Board schematic (power portion) I think my board has a problem in PLL function and Power connection is correct or not (?) Can you review where is wrong connection ? Thank you Michael

Hi Michael, I am not power expert but I do noticed 2 main concern that alert me. FPGA RREF pins (Reference resistor for fPLL, IOPLL, and transceiver) is not connected to 2Kohm Resistor then to GND. Highly suspect PLL functionality failure is caused by RREF pins connection. FPGA Vref power supply pins : You may need to power up Vref pins depends on input IO pins usage (depends on IO standard) It's very dangerous if there is still issue with your board design. I strongly recommend you to perform full board schematic review again. Below is one good reference doc that can help you on board schematic review https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf Thanks. Regards, dlim

Cyclone 10 GX DisplayPort Rx | Altera Community

23 Replies

Deshi_Intel
Regular Contributor
4 years ago
Hi Michael,

Good news indeed !

So you are saying there is wrong DP signal assignment on your custom board ? Then you fixed it.

After that, is your custom board DP functionality working now ? or you still face some issue ?

Thanks.

Regards,
dlim
Michael2021
Occasional Contributor
4 years ago
I removed the repeater chip control (using PIC Controller firmware : was blocked training sequence)

and DP rx_serial_input port was assigned reverse (But Still I can't understand)

Now my custom board works good.

My next concern is how to increase 8.1G data rate. There is no option in Non GPU DisplayPort mode (Max 5.4G)

Thank you

Michael
Deshi_Intel
Regular Contributor
4 years ago
Hi,

Are you using very old Quartus version ?
I do a quick check on v20.4 Quartus Pro and I can see that C10 GX FPGA DP IP did support till 8.1G.

The other thing to take note is for 8.1G (HBR3) support, it recommended to use repeater/retimer for DP Rx side. Checkout below link page 8, table 8
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an_745.pdf

Thanks.

Regards,
dlim
Michael2021
Occasional Contributor
4 years ago
Thank you so much

Michael
- Michael2021
  Occasional Contributor
  4 years ago
  Hello
  
  I am doing DisplayPort comparability test.
  
  I found Desktop PC included Video card detect right resolution but the some laptop PC doesn't output video signal due to detect wrong resolution. My DP core is non GUP mode so I can't find the problem. I guess the reason of trouble is in DP Link training sequence.
  
  Can you recommend how to solve the problem ?
  
  Thank you
  
  Michael
Deshi_Intel
Regular Contributor
4 years ago
Hi Michael,

You are welcome !

FYI... Intel support structure is on a case by case basic.

For now, I am setting this case to closure but feel free to post new forum thread if you still have new enquiry in future.

Thanks.

Regards,
dlim
- Michael2021
  Occasional Contributor
  4 years ago
  Thanks
  
  I can't find how to open new case ?

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Cyclone 10 GX DisplayPort Rx

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