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mattsqp
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4 months ago

Cyclone 10 GX Dev Kit: IOPLL not locking when using CvP mode

Hi everyone, I'm working with a simple CvP-based design on the Cyclone 10 GX Development Kit. My design is based on the official CvP example design, with a small modification: I've added an IOPLL th...
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mattsqp
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1 month ago

Hi Farabi,

Thank you for your answer. I can ensure that both the .periph.jic and .core.rbf are generated from the same Quartus project. However, I've noticed that even minor changes, like changing a blinky counter in the FPGA logic (with no changes to the periphery or PCIe configuration), result in a slightly different periphery image. I think this behavior is expected as Quartus embeds some metadata in the bitstream or the place and route algorithm is not fully deterministic.

This would mean that we need to keep the specific periphery image (that is flashed at the customer site) under strict revision control, and all subsequent core images would have to be built against the exact same periphery image. Is that the recommended workflow?

Thank you and best regards,
Matthias