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Altera_Forum's avatar
Altera_Forum
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11 years ago

cyclon 4 gx pcie card is not detection problem

Hi all,

i am doing pci express by using cyclone 4 gx device (ep4cgx75f23i7). when i inserted the card into the pcie slot and restarted it .but my pc is not recognising it.

To check the problem i am using signal tap 2. when i am monitoring some signals like

clocks: fixedclk, pld_clk, clb_clk, like all clocks are coming and pll_locked,rx_freq_locked are coming.

resets : pcie_rstn, npor,rx_digitalreset,app_rstn all reset signals are coming and reset status signal is also zero.

But LTSSM signal is toggling bwn 0 and 2 and it is not going to POLLING.CONFIG mode.

and when i monitored test out signal nothing is coming.

so, please suggest me what to do in my case, i am not finding where the exact problem is?

is there any chances to go wrong in ip core or the problem is in my custom board?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi naresh,

    which PCIe Version are you using? If possible try another PC and look into your Bios. I think I had a similar problem too. Maybe I remember what I exactly did ;)

    Which Quartus Version are you using?

    Kr,

    Florian
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    hi Florian,

    i am using quartus 13.1 and in that ip compiler for pci express v13.1 is using.is there any problem with this version.I tried with another pc also but remain same.but when i restaring my pc with pcie card is present then it is going to hang. actually, for generation of fixed clock and reconfig clock i am using 64 mhz clock from my board.i think this is not an issue,any sugggesion?

    here i am attaching the signal tap 2 waveforms please see it
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    For IP Compiler for PCI express:

    1) The maximum frequency of reconfig_clk is 50 MHz. Your reconfig_clk should not exceed 50MHz.

    2) fixedclk frequency must be 125MHz.

    3) Both fixedclk and reconfig_clk must be free running, it can’t be generated from the 100MHz refclk or its derived clocks.