CXL Base Hard IP CPI interface question

Hi there,

This is an interesting question. According to my discussion with the IP team, the reason for this phenomenon is not caused by the IP itself. The soft logic part of the CXL IP simply converts the packets received from the R-Tile. When the R-Tile sends them over, there are four response channels, but the CXL IP converts them into the standard CPI interface. Therefore, the routing logic is provided by the R-Tile, and the CXL IP just follows it.

Best regards,
WZ

Hi there,

I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.

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Best regards,

WZ

Hi，WZ2：

There is a description at page 96 of " Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP User Guide ( 763328)".

" The Ingress (A2F) direction has two CPI instances, where each instance has one global physical channel, one DATA physical channel, two REQ physical channels, and four RSP physical channels. The FPGA soft logic runs at a lower frequency than the hardened RTile, hence multiple instances and physical channels are required to rate match the available link bandwidth "

That is to say ,the four RSP physical channels are for transfer data in parallel.

Hi there,

What you said describes the structure, connection requirements, and credits of the Ingress (A2F) direction data transmission system. The focus is on the design of multiple instances and multiple channels, as well as the initialization and management of credits. However, it cannot be completely understood as the four RSP physical channels are for transfer data in parallel. The data channels transmit relatively independently from each other.

Best regards,

WZ