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javen1122
New Contributor
New ContributorCXL Base Hard IP CPI interface question
Why does the CPI interface of CXL Base Hard IP have 8 rsp_rxcrd_valid and rsp_rxcrd_protocal_id signals? It only has 2 ingress and egress channel.According to my understanding，It should have 2 rsp_rx...
javen1122New Contributor
New ContributorHi，WZ2：
There is a description at page 96 of " Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP User Guide ( 763328)".
" The Ingress (A2F) direction has two CPI instances, where each instance has one global physical channel, one DATA physical channel, two REQ physical channels, and four RSP physical channels. The FPGA soft logic runs at a lower frequency than the hardened RTile, hence multiple instances and physical channels are required to rate match the available link bandwidth "
That is to say ,the four RSP physical channels are for transfer data in parallel.
