Forum Discussion
Altera_Forum
Honored Contributor
11 years agoOK, the timing violations seem to be "harmless" as they were associated with the the pattern generator. Altera has set a false path on them in their cyclone v gs reference designs (http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html) as well:
set_false_path -from
set_false_path -from
set_false_path -from
set_false_path -from
set_false_path -from
set_false_path -from .gpll~PLL_OUTPUT_COUNTER|divclk}] -to .gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch.inst_av_pcs_ch|inst_av_hssi_8g_rx_pcs|wys|rcvdclkpma}]
set_false_path -from .gpll~PLL_OUTPUT_COUNTER|divclk}] -to .gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch.inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk}]
(Besides, they showed up without the 8b/10b interface, and there, the test ran fine....) So Back to the original problem: What am I doing wrong?