Hello, I have a very small board containing ethernet phy, sdram and cyclone III fpga only. The fpga upload is done from another board, which has microcontroller on it, using passive serial mode. The .sof upload is easy, I enable TTF file generation in Quartus and give that generated code to the microcontroller. Now the difficult part is Nios upload. I don't have neither EPCS nor CFI flash, but I have 8bit interface with microcontroller with some control signals, so I need other methods to upload Nios .elf file to the system, instead of epcs and cfi methods described in manual. One of the ideas would be to place reset vector into onchip memory where I would place a small program, that copies software into sdram, but I am not sure if the option enabling memory initialization from .hex is directly compiled into the .sof or not. Are there any solutions? Thanks.

Yes if you specify on the on-chip ram block to use a specified .hex file, it will be included in the .sof configuration and will be available as soon as the FPGA switches to user mode. Just be sure that your software is compiled into the correct .hex file, and that you compile the Quartus project after the .hex file has been updated. If the Quartus project is already compile, you should only need to run the assembler to update a .sof when you change the contents of the .hex file.

So I should put the reset vector to the on-chip ram, then it should start the bootloader where I copy the data to sdram and jump to the start address?

Yes, exactly. Just ensure that your bootloader software project is configured to place the code in the on-chip ram. application note 458 (http://www.altera.com/literature/an/an458.pdf) is about designing custom boot loaders and could help you in this task.

Right, but now the interesting question: what if Nios received reset? It'll jump to bootloader which will wait for a new binary file then?

Yes. All the bootloaders I know re-load the application on reset. In theory you could change the bootloader code so that it detects a reset condition and chooses to directly jump to the application instead of waiting for a new binary file. You should be vary careful with this though, as all the static variables with initialization will keep the value they had before reset instead of being reinitialized to their default value. This could break your code (or some drivers).

custom Nios bootloader | Altera Community

15 Replies

Altera_Forum
Honored Contributor
14 years ago
Well, that's actually strange, because I am writing data from 0x00800000, which is SDRAM_BASE. It always stops writing at 0x00800864. I am also using SPI interrupt to get byte and then write it to SDRAM.
Altera_Forum
Honored Contributor
14 years ago
How can you be using the SPI interrupt in the bootloader, when the interrupt vector address is in SDRAM - where you are loading the code to.

I'd have thought you'd need to run the boot loader with interrupts disabled (polling for status).

Also, where is your bootloader's stack (if the code actually uses one). If that is in SDRAM you might be writing over the stack.

It ought to be possible to write a bootloader (in C) that has almost no memory accesses. I couldn't stop the function prologue saving registers - they are the only references to %sp in my entire hdlc and mtp2 engines.
(gcc would need a rebuild to let me use %sp as a general register!)
Altera_Forum
Honored Contributor
14 years ago
Hm, I've set all the vectors to on_chip ram except the exception one. Just a minute ago, I've managed to run the bootloader using SPI status register polling. Now I'll try to use interrupts if possible.
Altera_Forum
Honored Contributor
14 years ago
Why bother using interrupts?
The processor isn't doing anything else is it?
Altera_Forum
Honored Contributor
14 years ago
Using interrupts is elegant solution :) but anyway, it doesn't work as You've said. I've left the bootloader to poll bytes from SPI.

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custom Nios bootloader

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