Custom Component, Write not working

Where is the chipselect signal in your IP ?

yes the avalon specification available here

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=avalon spec

does not include the chipselect input anymore.

as your datawidth is 32 bit, i recommend to monitor the byteenable signals as well they tell you what part of your write date is valid.

next thing is

if avs_s0_read_n = '0' then

avs_s0_readdata <= std_logic_vector(fixA_array(P_line,P_column)) ;

so your read data is 1 clock delayed valid but i see no waitrequest but a read wait time of 1

maybe the data you expect is avaiable after your access is finished.