Honored Contributor
Honored ContributorThat was how I initially implemented the design but the colors are not mixing correctly. I need to be able to adjust the levels of red, green and blue independently. That is why I considered the CSC which gives me the opportunity to add a summand (+ or -) to the end result and to control this in runtime from SOPC.
I have figured out the format of the 32-bit summand and co-efficient registers. In case it will be helpful to others, here is my understanding: The megafunction setup in SOPC defines by default 8 fractional bits. You can change this in the wizard. To calculate the value in the register each fractional bit continues the 8-4-2-1 sequence for the whole number part, i.e. msb of fractional bit = 1/2, next msb = 1/4, next msb = 1/8, etc. So for example, to write 1.5 in 32-bit reg is 0x00000180 Negative numbers are the 2's complement of this value. Compute the 2's complement on the whole 32-bit reg. For example, -1 would be written as 0xFFFFFF00. I still have a problem with not being able to stop the CSC which I now believe to be a problem with my system design. I am using pipeline bridges between the DDR2 RAM and the DIL/VFB cores. Should these use the core clock or the DDR2 clock?
