Forum Discussion

nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Critical Warning: PLL clock

Hello We are porting Arria ii gx Nios processor in ddr2 IP and ddr2 clock feed from PLL C0 and PLL IP directly connected from FPGA clock I am facing some below critical warnings I google this ki...
Memory
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

The warning is pretty self explanatory. It's not an SDC issue. As the message says, you're not driving the PLL from a dedicated clock input pin or from another PLL.