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Altera_Forum
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12 years ago

Converting FPGA design to VLSI design

I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement. Ho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Hi,

just to mention.. If the intention is to transfer the FPGA to an ASIC, maybe it's worth having a look at the hardcopy option offered by ALTERA...

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Thanks for your reply. How can I get the hardcopy?