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Altera_Forum
Honored Contributor
Honored ContributorConverting FPGA design to VLSI design
I have a design which has been verified on Alter FPGA. Now I'm going to convert this design to VLSI design. I will use Cadence RTL Compiler for synthesis and SOC Encounter for route and placement. Ho...
Altera_ForumHonored Contributor
Honored ContributorMultipliers should be available with cadence, for FFT you need to look for an alternative IP or design it yourself. Altera FFT is protected IP and can't be used with other tools for synthesis.
