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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

control packets issue in dsp builder

Hi

I am working on video and image processing project.

I am using quartus II v6.0 and dsp builder.

I have used deinterlacer, chroma resampler, color space converter and scaler megacore function between two avalon streaming interfaces as it is shown in the figure.

I want to process video data packets only, so I have to import a custom logic block(vhdl or verilog file) in between deinterlacer and chroma resampler, but the problem is I donot know before the video packets either the control packets are coming or not.

How Custom logic block(vhdl or verilog file) can differentiate between video and control packets??????

I donot know how to handle this issue of control packets!!!!!!!!

If you have any idea please let me know.

Thank You

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    AoA Rizwan sb

    I am Rafi from Lahore Pakistan. I can not any help for you. Because i am a biggner in FPGA.

    If you can my help? please tell me about Quartus II, SOPC Builder and Nios II Eclipse Plateform.

    When i press the button "submit reply" then occure error message

    "please remove e-mail addresses from your message, then you will be able to submit your post."

    my email address is "srafi56 at the rate of yahoo dot com"

    Thank you

    Rafi