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Altera_Forum's avatar
Altera_Forum
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8 years ago

connecting 32 bit data to 128 bit data with avalon

I think it maybe a silly problem but I can't get it work. I want to connect my master with 32 bit datawidth to a ddr controller with 128 datawidth using qsys. But when I simulate it in modelsim, it s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I've had similar issues with the Altera DDR3 controller getting stuck and never asking for data when connected to Avalon-MM interconnect fabric - they don't seem to like each other very much.

I made the attached Qsys IP core which allows narrow masters to connect to wide slaves. It seems to do the trick for me at least, so might be worth a try. Just select the Qsys parameters for the module to ensure that the output interface sideband signals match the DDR signals so that no fabric is inserted between.