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Altera_Forum
Honored Contributor
Honored ContributorConfliction on reading and refreshing request on DDR2 SDRAM Controller
I am using the DDR2 SDRAM Controller generated by Megawizard of Quartus9.1. The basic reading and writing request can successfully processed by controller, but, when the reading request is en...
Altera_ForumHonored Contributor
Honored ContributorActually, I am using the DDR2 SDRAM Controller 9.1 rather than high performance controller. As I know from the "supports", the commands fifo depth is 3 for this kind of Controller. Once the FIFO is full, the local_ready signal will be deasserted.
However, in the case I encountered with, the ready was never deasserted and there is one cycle of X. After that, the Controller did not response to read and write request any more. Is there other operations that may cause this problem?
