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Altera_Forum's avatar
Altera_Forum
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15 years ago

Confliction on reading and refreshing request on DDR2 SDRAM Controller

I am using the DDR2 SDRAM Controller generated by Megawizard of Quartus9.1. The basic reading and writing request can successfully processed by controller, but, when the reading request is en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If you are using the HPCII then the controller has a command fifo 8 commands deep. If the memory is busy refreshing then this fifo may get full and the controller will deassert local_ready at which time you cant issue any further commands.

I've never seen the X after refresh is finished however??