Altera_ForumHonored Contributor15 years agoCompiling Encrypted Design Files I'm attempting to compile the Megacore Triple Speed Ethernet module for sumulation using Active HDL. I want to compile the library files into a resource library and attach that to my simulation. Ho...Show More
Altera_ForumHonored Contributor15 years agoDid you notice the eda tab in the MegaWizard for TSE? It's about your problem.
Recent DiscussionsCORDIC ATan2 Failed to GenerateWhere is High Speed Transceiver Demo Design in FPGA Wiki ?Technical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay CalibrationI want to use a lot of 10GBase-R PHY on an Agilex 5 EJESD240B - No license