Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi, using yr suggestion.. I can compile the <file name>.vho into the modelSim.
Now I tried to compile the <file name_tb>.vhd into my project also has no problem. When I run simulation using this IP generated testbench file, it mentioned of fatal error. the error message is as below: # Fatal error in Process memory at C:/altera/91/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39243# Cannot continue because of fatal error.# HDL call sequence:# Stopped at C:/altera/91/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd 39243 Subprogram read_my_memory# called from C:/altera/91/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd 40978 Process memory Do I need to modify the generated testbench file before compiled it in modelSim in order to run simulation?