Comparison between DDR2 controller and high performance controller

FvM, Thanks for the prompt response. I am targeting a Stratix II GX device and currently have a working model of the DDR2 Controller (250 MHz, 64-bit data bus), which is based on an older version (7.1) of Altera's reference design. I suspect that it is using only half the data bandwidth since local bus, though 128-bit wide, carries 2 64-bit duplicate values. My application needs to squeeze out as much storage and performance as possible. I am happy with speed performance so far, but I wonder if non-HP design is restricting me to only half the storage (256 MB SDRAM providing only 128 MB capacity).