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Altera_Forum's avatar
Altera_Forum
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8 years ago

Commands to modular SGDMA Read Master for a single and burst read ?

Hi,

I'm trying to use the modular SGDMA Read Master to allow my custom IP to read from On-Chip and SDRAM in my QSYS project. However, I'm having trouble figuring out how to interact with this Read Master in order to it have perform a read or burst read. All I have for documentation is the PDF (attached) from the modular SGDMA wiki but it's not complete.

Below is my basic state machine for a single read and the simulation results are attached. I can read the correct data (0xFFFFFFFF) but I never see the done strobe while response_source_valid is asserted.

Does anyone have any idea what I'm doing wrong ? Also, what would the steps be to perform a burst read ?

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always @ (posedge clk_in or negedge reset_n_in) begin

if (~reset_n_in) master_read_FSM <= s0;

else case (master_read_FSM)

s0 : begin

dma_read_master_0_command_sink_data_out <= 256'h0;

dma_read_master_0_command_sink_valid_out <= 1'b0;

dma_read_master_0_data_source_ready_out <= 1'b0;

dma_read_master_0_response_source_ready_out <= 1'b0;

master_read_FSM <= cmd_go_pulse ? s1 : s0;

end

s1 : begin

master_read_FSM <= dma_read_master_0_command_sink_ready_in ? s2 : s1 ;

end

s2 : begin

dma_read_master_0_command_sink_data_out[31:0] <= 32'h08000000; // address 31:0

dma_read_master_0_command_sink_data_out[140:109] <= 32'h0; // address 63:32

dma_read_master_0_command_sink_data_out[63:32] <= 32'h00000004; // length

dma_read_master_0_command_sink_valid_out <= 1'b1;

master_read_FSM <= s3 ;

end

s3 : begin

dma_read_master_0_command_sink_valid_out <= 1'b0;

dma_read_master_0_data_source_ready_out <= 1'b1;

dma_read_master_0_response_source_ready_out <= 1'b1;

master_read_FSM <= dma_read_master_0_data_source_valid_in ? s4 : s3;

end

s4 : begin

slave_data_0_out <= dma_read_master_0_data_source_data_in;

master_read_FSM <= (dma_read_master_0_response_source_valid_in && dma_read_master_0_response_source_data_in[2]) ? s0 : s4;

end

default : master_read_FSM <= s0;

endcase

end

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Appreciate the help.

Arsen

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    In your test bench you may need to create structures for the DMA descriptors and then drive them to the DMA engine depending on the SRC valid and ready signals. take a look at the code snippet below.. It should give you an idea on how to write a TB for DMA 

    
reg   read_addr_l;
reg   length;
reg    tx_channel;
reg         gen_sop;
reg         gen_eop;
reg         stop;
reg         reset;
reg    read_burst_count;
reg   read_stride;
reg    tx_error;
reg         early_done_enable;
reg   read_addr_h;
reg  reserved;
reg  dma_desc;
//assign values to desc fields.
assign reserved          = 115'h0;
assign gen_sop           = 1'b1;
assign gen_eop           = 1'b1;
assign stop              = 1'b0;
assign reset             = 1'b0;
assign read_addr_h       = 32'h0; // assign your read address high bits here
assign read_addr_l       = 32'h0; // assign your read address low bits here
assign length            = 32'h0; // assign length of DMA transfer
assign tx_channel        = 8'h0;  // assign tx channel here
assign read_burst_count  = 8'h0;  // For burst transfers set value here
assign early_done_enable = 1'b1;
assign dma_desc = {reserved, read_address_h, early_done_enable, tx_error,
                   read_stride, read_burst_count, reset, stop, gen_eop, gen_sop,
                   tx_channel, length, read_address_l};
always@(posedge clkin or negedge reset_n_in) begin
if(!reset_n_in) 
   dma_desc <= 256'h0;
   snk_command_data <= 256'h0;
else begin
   if(src_ready && src_valid) begin  // check if source is ready and valid, then send desc data to DMA engine
      snk_command_data <= dma_desc; 
        if( )
...
...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Thanks for the response eapenabrm. I don't fully understand what you mean. I'm trying to use the Read Master of the modular SGDMA by itself as an Avalon MM Read Master for my custom IP. My problem is that I don't know how to drive the Read Master module to perform a single read or burst read. The Read Master has a data source valid and ready as well as response source valid and ready. The valid signals are outputs from the Read Master while the ready signals are inputs which I need to drive. I'm not sure which SRC valid and ready signals you're referring to and how you can be monitoring both. Do you mind clarifying what you mean ?

    Just a side note, I also tried using the altera provided MM master template but couldn't get it to work in simulation. The waitrequest signal seemed to be stuck high forever.