Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi,
In your test bench you may need to create structures for the DMA descriptors and then drive them to the DMA engine depending on the SRC valid and ready signals. take a look at the code snippet below.. It should give you an idea on how to write a TB for DMA
reg read_addr_l;
reg length;
reg tx_channel;
reg gen_sop;
reg gen_eop;
reg stop;
reg reset;
reg read_burst_count;
reg read_stride;
reg tx_error;
reg early_done_enable;
reg read_addr_h;
reg reserved;
reg dma_desc;
//assign values to desc fields.
assign reserved = 115'h0;
assign gen_sop = 1'b1;
assign gen_eop = 1'b1;
assign stop = 1'b0;
assign reset = 1'b0;
assign read_addr_h = 32'h0; // assign your read address high bits here
assign read_addr_l = 32'h0; // assign your read address low bits here
assign length = 32'h0; // assign length of DMA transfer
assign tx_channel = 8'h0; // assign tx channel here
assign read_burst_count = 8'h0; // For burst transfers set value here
assign early_done_enable = 1'b1;
assign dma_desc = {reserved, read_address_h, early_done_enable, tx_error,
read_stride, read_burst_count, reset, stop, gen_eop, gen_sop,
tx_channel, length, read_address_l};
always@(posedge clkin or negedge reset_n_in) begin
if(!reset_n_in)
dma_desc <= 256'h0;
snk_command_data <= 256'h0;
else begin
if(src_ready && src_valid) begin // check if source is ready and valid, then send desc data to DMA engine
snk_command_data <= dma_desc;
if( )
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