Clocked Video Input register discrepancy

Had anyone else noticed the discrepancy between the VIP reference design status register (offset 2) for Clock Video Input and the VIP documentation?

The reference design code shows 10 bits with the overflow setter at bit 8 and overflow assert on bit 9.

The documentation says 10 bits but the overflow setter and assert both share bit 9.

Lower bits get offset, so I'm not sure of the signals I can expect from them.