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JLee25's avatar
JLee25
Icon for Contributor rankContributor
4 years ago

Clocked Video Input Clipping

Hi,

I am using the CVI with 12G SDI for my system.

The device is C10GX220 and Quartus Pro 19.2.

The platform designer connection is,

CVI -> Stream Cleaner -> Scaler -> frame buffer -> CVO..

I found 2 issues,

1. When input is 3G-SDI, the resolution will reported as 960 x 1080

2. When input is 12G-SDI, the data was clipped...

Attached is the Avalon bus for CVI data.

How can I fix it?

BRs,

Johnson

4 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Johnson,


    As I understand it, you have some inquiries related to using 12G SDI with CVI II. For your information, you may try to refer to the following A10 example design with 12G SDI and CVI II to see if it is helpful:


    https://fpgacloud.intel.com/devstore/platform/19.2.0/Pro/intel-arria-10-gx-device-multi-rate-sdi-ii-pass-through-using-video-image-processing-pipeline-reference-design/


    This design is created for A10 device but there should be no problem to port over to C10GX device.


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin


    • JLee25's avatar
      JLee25
      Icon for Contributor rankContributor
      4 years ago

      Hi CP,

      Thank you!

      I download the project and looks at it carefully.

      But I am not to find any problem in the settings.

      The differences I noticed is the vid_std bus width, it's 12-bit in A10 but only 3-bit in C10.

      And the Qsys is runninng at 200MHz, higher than mine.

      I increase the clock but the status remain the same.

      Here I change the configuration of the CVI-II, to disable "matching data packet to control by the clipping".

      The CVI output avalon streaming is working after disable the function.

      The down stream component, stream cleaner" trigger the ready signal, but the output did not provide a valid streaming protocol, sop, eop..

      The CVI just keep toggling data_valid..

      Any suggestions?

      BRs,

      Johnson

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago


    Hi Johnson,


    To further narrow down the issue, can you try to create simple design by replacing your CVI with TPG? Then run through Modelsim simulation to see the rest of the components are working as expected. This is to narrow down the location to CVI.


    Another thing to try out is to port the example design to C10 device and test on your board with the same SDI input to see if there is any difference. If this is working, then you can further customize from here.


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin


  • JLee25's avatar
    JLee25
    Icon for Contributor rankContributor
    4 years ago

    Hi CP,

    I create the design and test on my board.

    Strange thing is I am not able to get a reliable resolution detection on 12G.

    The resolution bit is not stable and will switch between valid or invalid.

    The line will change between 2160 or 2158...

    Any comments?

    BRs,

    Johnson