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JLee25's avatar
JLee25
Icon for Contributor rankContributor
4 years ago

Clocked Video Input Clipping

Hi, I am using the CVI with 12G SDI for my system. The device is C10GX220 and Quartus Pro 19.2. The platform designer connection is, CVI -> Stream Cleaner -> Scaler -> frame buffer -> CVO....
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Johnson,


As I understand it, you have some inquiries related to using 12G SDI with CVI II. For your information, you may try to refer to the following A10 example design with 12G SDI and CVI II to see if it is helpful:


https://fpgacloud.intel.com/devstore/platform/19.2.0/Pro/intel-arria-10-gx-device-multi-rate-sdi-ii-pass-through-using-video-image-processing-pipeline-reference-design/


This design is created for A10 device but there should be no problem to port over to C10GX device.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin


JLee25's avatar
JLee25
Icon for Contributor rankContributor
4 years ago

Hi CP,

Thank you!

I download the project and looks at it carefully.

But I am not to find any problem in the settings.

The differences I noticed is the vid_std bus width, it's 12-bit in A10 but only 3-bit in C10.

And the Qsys is runninng at 200MHz, higher than mine.

I increase the clock but the status remain the same.

Here I change the configuration of the CVI-II, to disable "matching data packet to control by the clipping".

The CVI output avalon streaming is working after disable the function.

The down stream component, stream cleaner" trigger the ready signal, but the output did not provide a valid streaming protocol, sop, eop..

The CVI just keep toggling data_valid..

Any suggestions?

BRs,

Johnson