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Altera_Forum
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11 years ago

Clock Video Output is not working in Cyclone III FPGA

My Design consists of a clocked video output set to a resolution of 1024x768 @60Hz 65 MHz pixel clock. The data input is from the test pattern generator ip from the VIP block. When i build the qsy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Check frame size you need. I see frame size generating from TPG is 1024x768, but CVO configured as 1920x1080