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Altera_Forum
Honored Contributor
Honored ContributorClock Assignment on (X,Y) region for DDR3 SDRAM Controller with UniPHY IP in Arria V
can anyone please help explain how does the tool go about the (x,y) coordinate of region to decide which fractional pll the clock will use to output clock to logic? I am targeting Arria V G...
Altera_ForumHonored Contributor
Honored ContributorHi,
You can try to lock the PLL location through Assignment Editor. Find the PLL node in the RTL, and then locate in Assignment Editor and set the location.
