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Altera_Forum
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17 years ago

Clamshell Top and Bottom Device

Hi There Has anyone there got idea on clamshell top and bottom device. In my case the DDR2 device on altera board(StratixIIGX) has 14 address lines per clamshell with 3 bank address bits. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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The address and bank address lines are shared between both devices in the clamshell, with the chip select signal used to selectively write to one device or the other or both.

The data bus is 16-bits wide (8 bits per device). But the control signals for both the device have got different pin assignments.

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Sorry, I still don't understand. The control signals can be either shared, which to my opinion means, they connect to the same FPGA pin, each, or separate, connecting to different FPGA pins. In the latter case you need two controller instances.

By the way, I 'm unable to identify any "Altera CNIC 2a" board.