Clamshell Top and Bottom Device

Thanks FVM,

I am using Altera CNIC 2a, which is based on StratixIIGX device, which has four independent banks of 256MB DDR-II. The DDR2 device on the board is MT47H128M8HQ-3:E (333MHz).

The address and bank address lines are shared between both devices in the clamshell, with the chip select signal used to selectively write to one device or the other or both.

The data bus is 16-bits wide (8 bits per device). But the control signals for both the device have got different pin assignments.

Since the memory is one, with 16 bit datapath, I doubt whether we really need to have two instances of controller. Suggest how to handle it.

Regards

Harsh Bandil