Ciii DDR2, Critical Warning

Critical Warning: Pin mem_clk[0] must have its Cyclone III Input Pin to Logic Array Delay 0 set to 0 (the delay chain is currently set to 1)

Critical Warning: Read Capture and Write timing analyses may not be valid due to violated timing model assumptions.

how can i fix this warning?

i am using TimeQuest Timing Analyzer as the default timing analyzer.

thanks.