Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI believe it is.
I constrained my 24 MHz input clock and all PLL generated clocks with: create_clock -name {sys_clk_in} -period 41.666 -waveform { 0.000 20.833 } [get_ports {sys_clk_in}] derive_pll_clocks derive_clock_uncertainty and I made sure the megawizard generated files 'altmemddr_0_phy_ddr_timing.sdc' and 'cpu_0.sdc' are included in the project. Thanks Scott