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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can't find clock output pins of DDR

Hi, I have a NiosII design that contains a ddr_sdram core. When I moved from Quartus 9.0 to 9.1, it started giving me the following error: Error: DDR Post compile timing analysis failed...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

make the assignments in the assignment editor.

The fitter report should provide a name for your actual PLL instance.